Albert Wang, On-Chip
ESD Protection for Integrated Circuits – An IC Design Perspective, Kluwer Academic Publishers, Boston, 2002, ISBN:
0-7923-7647-1.
SELECTED
TOPICAL PUBLICARIONS
On-Chip
ESD Protection for RF/AMS ICs:
·
A.
Wang, L. Lin, X. Wang and H. Liu, “Emerging Challenges in ESD Protection for RF
ICs in CMOS”, Invited, to appear, J. of
Semiconductor, 2008.
·
X. Guan, G. Chen, L. Lin, X. Wang, Albert
Wang, L. Yang and B. Zhao, “A New ESD-Aware Power Amplifier Design Method”, Proc. IEEE ASICON, pp1363-1366, 2007.
·
Albert Wang, H.
Feng, R. Zhan, H.
Xie, G. Chen, Q. Wu, X.
Guan, Z. Wang and C. Zhang, “A Review on RF ESD Protection Design”,
IEEE Trans. Electron Devices, Vol. 52, No. 7, pp. 1304-1311, July 2005.
·
H. Xie, H.
Feng, R. Zhan, Albert
Wang, D. Rodriguez and D.
Rice, “A New Low-Parasitic Polysilicon SCR ESD
Protection Structure for RF ICs”, IEEE Electron Device Letters, Vol. 26,
No.2, pp.121-123, February 2005.
·
R.
Zhan, H. Feng,
Q. Wu, H.
Xie, X. Guan, G. Chen and Albert
Z. Wang, “ESDInspector: A New
Layout-level ESD Protection Circuitry Design Verification Tool Using A
Smart-Parametric Checking Mechanism”, IEEE
Trans. CAD of Integrated Circuits and Systems, Vol. 23, No. 10,
pp.1421-1428, October 2004.
·
G. Chen, H. Feng,
H. Xie, R. Zhan, Q. Wu, X. Guan, Albert Wang, K. Takasuka,
S. Tamura, Z. Wang and C. Zhang, “Characterizing Diodes For RF ESD Protection”,
IEEE Electron Device Letters, Vol. 25, No. 5, pp.323-325, May
2004.
·
H. Feng, R. Zhan,
G. Chen, Q. Wu and Albert Z. Wang,
“Electrostatic Discharge Protection for RF Integrated Circuits: New ESD Design
Challenges”, Analog Integrated Circuits and Signal Processing, An
International Journal, Vol. 39, Issue 1, pp. 5-19, April 2004.
·
R. Zhan, H. Feng,
Q. Wu and Albert Wang, “ESDExtractor: A New Technology-Independent CAD Tool for Arbitrary ESD
Protection Device Extraction,” IEEE Trans. CAD of Integrated Circuits
and Systems, Vol. 22, No. 10, pp.1362-1370, October 2003.
·
H. Feng, G. Chen,
R. Zhan, Q. Wu, X. Guan, H. Xie, Albert Wang and R. Gafiteanu, “A Mixed-Mode
ESD Protection Circuit Simulation-Design Methodology,” IEEE J. Solid-State
Circuits, V38, N6, pp.995-1006, June 2003.
·
H. Feng, R. Zhan,
Q. Wu, G. Chen and Albert Wang, “RC-SCR: A
Very-Low-Voltage ESD Protection Circuit in Plain CMOS,” IEE Electronics
Letters, V38, N19, pp.1099-1100, September 2002.
·
H. G. Feng, R. Y. Zhan, Q. Wu, G. Chen and Albert Z. Wang, “A Circular Under-Pad Multiple-Mode ESD Protection Structure for
ICs,”
IEE Electronics Letters, V38, N11, pp. 511 –513, May 2002.
·
H. G. Feng, K.
Gong, R. Zhan and Albert Wang, “A Novel all-Direction on-Chip Protection
Circuit,” IEICE Trans. Electron., Vol. E85-C, N3, pp.566-571, March
2002.
·
K. Gong, H. Feng,
R. Zhan and Albert Z. Wang, “A Study of Parasitic Effects of ESD Protection on
RF ICs,” IEEE Trans. Microwave Theory and Techniques, V50, N1,
pp.393-402, January 2002.
·
H. Feng, R. Zhan,
K. Gong and Albert Z. Wang, “A New Pad-Oriented Multiple-Mode ESD
Protection Structure and Layout Optimization,” IEEE Electron Device Letters,
V22, N10, pp.493-495, Oct. 2001.
·
K. Gong, H. G. Feng,
R. Y. Zhan and Albert Z. Wang, “ESD-Induced Circuit Performance Degradation in
RFICs,” Microelectronics Reliability,
V41, Issue 9-10, PERGAMON, Elsevier
Science, pp.1379-1383, September-October 2001.
·
Albert Z. Wang, H. G. Feng,
K. Gong, R. Y. Zhan and J. Stine, “On-Chip ESD Protection Design for Integrated
Circuits: an Overview for IC Designers,” Microelectronics Journal, Elsevier
Science, V32, Issue 9, pp.733-747, September 2001.
·
H. G. Feng, K.
Gong, R. Zhan and Albert Wang, “A Pad-Oriented Novel Electrostatic Discharge
Protection Structure For Mixed-Signal ICs,” in Advances in Systems Science:
Measurement, Circuits and Control, Edited by N. Mastorakis
and L. Pecorelli-Peres, Electrical and Computer
Engineering Series, WSES Press, 2001, pp.159-163.
·
H. G. Feng, K.
Gong, and Albert Z. Wang, “A Novel on-Chip Electrostatic Discharge Protection
Design for RFIC’s,” Microelectronics Journal, V32, Issue 3, Elsevier Science,
pp 189-195, March 2001.
·
Albert Wang and C. Tsay,
“On a Dual-Direction on-Chip Electrostatic Discharge Protection Structure,” IEEE
Trans. Electron Devices, V48, N5, pp.978-984, May 2001.
·
Albert Wang and C. Tsay,
“An on-Chip ESD Protection Circuit with Low Trigger-Voltage in BiCMOS Technology,” IEEE J. Solid-State Circuits, V36,
N1, pp.40-45, January 2001.
·
Albert Wang, C. Tsay,
and P. Deane, “A Study of NMOS Behaviors under ESD Stress: Simulation and
Characterization,” Microelectronics
Reliability, V38, Issue 6-8, PERGAMON,
Elsevier Science, pp.1183-1186, 1998.
·
Albert Wang, H.
Feng, R. Zhan, H. Xie, G. Chen and X. Guan, “RF
ESD Protection for VDSM Si Technology”, Proc. ECS
5th Int’l Semiconductor Technology Conference (ECS-ISTC),
2006.
·
G. Chen, H.
Feng, Albert Wang and Y.
Cheng, “Noise Analysis of ESD Structures and Impacts on a Fully-Integrated
5.5GHz LNA in 0.18mm SiGe BiCMOS”, Proc. IEEE 35th
European Microwave Conference, October 2005.
·
R. Zhan, H. Xie, H. Feng
and Albert Wang, “ESDZapper:
A New Layout-level Verification Tool for Finding Critical Discharging Path
under ESD Stress”, Proc. IEEE Asia
South Pacific Design Automation Conference (ASP-DAC), pp. 79-82,
2005.
·
H.
Xie, R. Zhan and Albert
Wang, “3D
Electro-Thermal Modeling of GGNMOS ESD Protection Structure”, Proc. IEEE Asia-Pacific Conf. on Circuits and Systems
(APC-CAS), pp.61-64, 2004.
·
G. Chen and Albert Wang, “Evaluating RF ESD
Protection Design: An Overview”, Proc.
IEEE 11th International Symp. Physical & Failure Analysis of ICs (IPFA), pp205-208,
2004.
·
G. Chen, H. Feng,
H. Xie, R. Zhan, Q. Wu, X. Guan, Albert Wang, K. Takasuka,
S. Tamura, Z. Wang and C. Zhang, “RF Characterization of ESD Protection
Structures”, Proc. IEEE Radio Frequency
Integrated Circuits Symp. (RFIC),
pp.379-382, 2004.
·
Albert Z. Wang, H. Feng,
G. Chen, R. Zhan, H. Xie, Q. Wu and X. Guan, “Key Aspects For ESD Protection
Design In ICs: Mixed-Mode Simulation And RF/Mixed-Signal ESD Protection,” IEEE
25th Int’l Conf.
on ASIC (ASICON), pp.1000-1005, 2003.
·
H. Feng, R. Zhan,
Q. Wu, G. Chen, X. Guan, H. Xie and Albert Z. Wang, “Mixed-Mode ESD Protection
Circuit Simulation-Design Methodology,” Proc. IEEE Int’l Symp.
Circuits and Systems (ISCAS), V1, pp.652-655, 2003.
·
H. Feng, R. Zhan,
G. Chen, Q. Wu, X. Guan, H. Xie and Albert Wang, “Bonding-Pad-Oriented on-Chip
ESD Protection Structures for ICs,” Proc. IEEE Int’l Symp.
Circuits and Systems (ISCAS), V 4, pp.741-744, 2003.
·
G. Chen, H. Feng
and Albert Wang, “A Systematic Study of ESD Protection Structures for RF ICs,” Proc.
IEEE Symp. RF Integrated Circuits (RFIC),
pp.347-350, 2003.
·
Albert Wang, “Recent Developments in ESD
Protection for RF ICs,” Proc. IEEE Asia South Pacific
Design Automation Conference (ASP-DAC), pp.171-178, 2003.
·
Albert Z. Wang, H. Feng, R. Zhan, G. Chen and Q. Wu, “ESD
Protection Design for RF Integrated Circuits: New Challenges,” Proc. IEEE Custom Integrated Circuits
Conference (CICC), pp.411-418, 2002.
·
K. Gong, H. Feng,
R. Zhan and Albert Z. Wang, “ESD-Induced Circuit Performance Degradation in
RFICs,” IEEE Proc. European Symp. Reliability of Electron Devices Failure Physics &
Analysis (ESREF), pp.1379-1383, 2001.
·
H. G. Feng, K.
Gong, R. Zhan and Albert Wang, “A Pad-Oriented Novel Electrostatic Discharge
Protection Structure For Mixed-Signal ICs,” Proc. WSES/IEEE Conferences: 5th
Circuits, Systems, Communications & Computers, pp.3421-3425, 2001.
·
H. G. Feng, K.
Gong, R. Zhan and Albert Wang, “A Novel all-Direction on-Chip Protection
Circuit,” Proc. IEEE/IEICE Int’l Symp. Signals,
Systems, and Electronics (ISSSE), pp.118-121, 2001.
·
H. G. Feng, K. Gong
and Albert Wang, “An ESD Protection Circuit for Mixed-Signal ICs,” Proc.
IEEE CICC, pp.493-496, 2001.
·
H. G. Feng, K. Gong
and Albert Wang, “A New Integrated Metal-Semiconductor Simulation Methodology
for on-Chip Electrostatic Discharge Protection Design Optimization“, Proc.
IEEE/IFIP World Computer Congress Int’l Conference on Design Automation,
pp.81–85, 2000.
·
H. G. Feng, K. Gong
and Albert Wang, “A Comparison Study of ESD Protection for RFIC’s: Performance
vs. Parasitics,” Proc. IEEE RFIC Symp., pp.235-238, 2000.
·
Albert Z. Wang, “A New Design for Complete
on-Chip ESD Protection,” Proc. IEEE Custom Integrated Circuits Conference, pp. 87-90, 2000.
·
Albert Z. Wang and C. H. Tsay,
“A Compact Square-Cell ESD Structure
for BiCMOS ICs,” Proc.
IEEE BCTM, pp. 46-49, 1999.
·
Albert Wang, C. Tsay and Q. Shan, “A Novel
Dual-Direction IC ESD Protection Device,” Proc.
IEEE 7th Int’l Symp. Physical and Failure
Analysis of Integrated Circuits, pp.151-155, 1999.
·
Albert Wang, C. Tsay,
J. Bielawski and L. DeClue,
“Design Optimization of a Practical ESD Protection Circuit by CAD: A Case
Study,” Proc. IEEE 13th UGIM Symp.,
pp. 116-119, 1999.
·
Albert Wang and C. Tsay,
“A Low-Triggering Circuitry for Dual-Direction ESD Protection,” Proc. IEEE
Custom Integrated Circuits Conference,
pp 139-142, 1999.
·
Albert Wang, C. Tsay, A. Lele
and P. Deane, “A Study of NMOS Behaviors under ESD Stress: Simulation
and Characterization,” Proc. IEEE 9th
European Symp. Reliability of Electron Devices
Failure Physics & Analysis, pp.151-155, 1998.
RF
Inductors:
·
C. Yang, F. Liu, T. L. Ren, L. T. Liu, G.
Chen, X. K. Guan, Albert Wang and Z. Yue, “Ferrite-Partially-Filled
on-Chip RF Inductor Fabricated Using Low-Temperature Nano-Powder-Mixed-Photoresist Filling Technique for Standard CMOS”,
Accepted, IEEE IEDM Digest, 2007.
·
C. Yang,
F. Liu, T. Ren, L. Liu, G. Chen, X. Guan, Albert Wang and H. Feng, “Ferrite-Integrated on-Chip Inductors for RF ICs “, IEEE
Electron Device Letters, Vol. 28, No.
7, pp652-655, July 2007.
·
F. Liu, C, Yang,
T. Ren, Albert Wang, J. Yu and L. Liu, “NiCuZn
Ferrite Thin Films Grown by a sol-gel Method and Rapid Thermal Annealing,” J.
of Magnetism and Magnetic Materials, V309,
Issue 1, pp.17-21, March 2007.
·
C. Yang, F.
Liu, T. Ren, L. Liu, H.
Feng, Albert Wang and H.
Long, “Fully Integrated Ferrite-Based
Inductors for RF ICs”, Sensors & Actuators: A. Physical, A 130-131, p365-370, 2006.
·
F. Liu, T.
Ren, C. Yang, L. Liu, Albert
Wang, and J. Yu, “NiCuZn Ferrite
Thin Films for RF Integrated
Inductors,” Materials Letter, Vol. 60, pp. 1403-1406, 2006.
·
T. Ren,
C. Yang, F. Liu, L. Liu,
Albert Z. Wang and X. Zhang,
“Equivalent Circuit Analysis of
an RF Integrated Inductor with
Ferrite Thin-Film,”
Journal of Semiconductors, Vol. 27,
pp. 511-515, 2006.
·
C. Yang,
F. Liu, T.
Ren, L. Liu,
H. Feng, Z. Albert Wang, H.
Long and J. Yu, “RF Integrated
Inductor with CoZrO Ferrite
Thin Film,” Journal of Semiconductors, Vol. 26,
pp. 2208-2212, 2005.
·
H. Long, Z.
Feng, H. Feng, Albert Wang, Tianling, Ren, Junbo Bao, Feng Liu, Chen Yang, Xiao
Zhang, “A New Modeling Technique for Simulating 3D Arbitrary Conductor-Magnet
Structures for RFIC Applications”, IEEE Tans. Electron Devices, Vol. 52, No.
7, pp. 1354-1363, July 2005.
·
H. Long, Z. Feng,
H. Feng and Albert Wang, “A Novel Accurate PEEC-based
3D Modeling Technique for RF Devices of Arbitrary Conductor-Magnet Structure,” Microwave
and Optical Technology Letters, V38, Issue 3, Wiley & Sons, pp.237-240,
August 2003.
·
C. Yang, F. Liu, T. Ren, L. Liu, G. Chen, X. Guan, Albert Wang and Z. Yue, “Ni-Zn Ferrite Film Coated on-Chip RF
Inductor Fabricated by A Novel Powder-Mixed-Photoresist
Spin-Coating Technique”, Proc. IEEE MTT-S
Int’l Microwave Symposium (IMS), pp465-468, 2007.
·
C. Yang, F. Liu,
T. Ren, L. Liu, G. Chen, X. Guan and Albert Wang, “Magnetic film inductors for
RF IC”, Proc. ECS
Int’l Semiconductor Technology Conference (ECS-ISTC), pp447-462, 2007.
·
C. Yang, F.
Liu, T. Ren, L. Liu and Albert
Z. Wang, “On-Chip Integrated Inductors with Ferrite
Thin-Films for RFIC”, Tech. Digest, IEEE
International Electron Devices Meeting (IEDM), pp225-228, 2006.
·
C. Yang, F. Liu, T. Ren, L. Liu and Albert Z. Wang, “On-Chip Integrated Inductors with Ni-Zn-Cu-Fe and Y-Bi-Fe Thin-Films for
RF IC”, Proc. 34th IEEE European
Solid-State Device Research Conf (ESSDERC), pp. 194-197, September 2006.
·
F. Liu, C. Yang, T. L. Ren, L. T.
Liu, H. G. Feng, Albert Z. Wang, H. B. Long and J Yu,
“Fully
Integrated Ferrite-Based Inductors for RF ICs”, Proc. IEEE
International
Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), Vol 1, pp.895 - 898, 2005.
·
H. Long, Z.
Feng, H. Feng, Albert Wang and T.
Ren, “L-SIMULATOR: A MAGPEEC-Based new
CAD Tool for Simulating
Magnetic-Enhanced IC Inductors
of 3D Arbitrary Geometry”,
Proc. IEEE International Symp. Circuits and Systems (ISCAS), Vol
5, pp. V-233/237, 2004.
·
H. Long, Z. Feng,
H, Feng and Albert Wang, “magPEEC:
Extended PEEC Modeling for 3D Arbitrary Electro-Magnetic Devices with
Application for M-Cored Inductors,” Proc. IEEE Symp.
RF Integrated Circuits (RFIC), pp.251-254, 2003.
·
H. Feng, G. Jelodin, K. Gong, R. Zhan, Q. Wu, C. Chen and Albert Wang,
“Super Compact RFIC Inductors in 0.18mm CMOS with
Copper Interconnects,” Proc. IEEE Microwave Symposium Digest, 2002, IEEE
MTT-S International, V1, pp. 553 –556, 2002.
RF/AMS
ESD Protection Circuit Design Method:
·
X. Guan, G. Chen, L. Lin, X. Wang, Albert
Wang, L. Yang and B. Zhao, “A New ESD-Aware Power Amplifier Design Method”, Proc. IEEE ASICON, pp1363-1366, 2007.
·
H. Xie, R. Zhan, H. Feng, G. Chen, Albert
Wang and R. Gafiteanu, “A 3D Mixed-Mode ESD Protection Circuit
Simulation-Design Methodology”, Proc. IEEE Custom Integrated Circuits Conference
(CICC), pp243-246,
2004.
· R. Zhan, H. Feng, Q. Wu, H. Xie, X. Guan, G. Chen and Albert Z. Wang, “ESDInspector: A New Layout-level ESD Protection Circuitry Design Verification Tool Using A Smart-Parametric Checking Mechanism”, IEEE Trans. CAD of Integrated Circuits and Systems, Vol. 23, No. 10, pp.1421-1428, October